W311HT datasheet(15/19 Pages) CYPRESS

15 / 19 page

W311

Document #: 38-07703 Rev. **

Page 15 of 19

AC Electrical Characteristics

TA = 0°C to +70°C, VDD = 3.3V±5%, VDD = 2.5V±5%fXTL = 14.31818 MHz

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output; Spread Spectrum is disabled.

Notes:

5. X1 input threshold voltage (typical) is 3.3V/2

6. The W311 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;

this includes typical stray capacitance of short PCB traces to crystal.

7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

Crystal Oscillator

VTH

X1 Input Threshold Voltage[5]

VDD = 3.3V

–

1.65

–

CLOAD

Load Capacitance, Imposed on

External Crystal[6]

–18

–

CIN,X1

X1 Input Capacitance[7]

Pin X2 unconnected

–

Pin Capacitance/Inductance

CIN

Input Pin Capacitance

Except X1 and X2

–

COUT

Output Pin Capacitance

–

LIN

Input Pin Inductance

–

DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% (continued)

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

CPU Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition

/Comments

CPU = 66.6 MHz CPU = 100 MHz

CPU = 133 MHz

Unit

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Period

Measured on rising edge at

1.25

–

15.5

–

10.5

7.5

–

8.0

High Time

Duration of clock cycle

above 2.0V

5.2

–

3.0

–

1.87

–

Low Time

Duration of clock cycle

below 0.4V

5.0

–

2.8

–

1.67

–

Output Rise Edge

Rate

Measured from 0.4V to

2.0V

1–

–

V/ns

Output Fall Edge

Rate

Measured from 2.0V to

0.4V

1–

–

V/ns

Duty Cycle

Measured on rising and

falling edge at 1.25V

–

tJC

Jitter,

Cycle-to-Cycle

Measured on rising edge at

1.25V. Maximum

difference of cycle time

between two adjacent

cycles.

–

250

–

250

–

250

tSK

Output Skew

Measured on rising edge at

1.25V

–

175

–

175

–

175

fST

Frequency

Stabilization from

Power-up (cold start)

Assumes full supply

voltage reached within

1 ms from power-up. Short

cycles exist prior to

frequency stabilization.

––

–

AC Output

Impedance

Average value during

switching transition. Used

for determining series

termination value.

–20

–

Ω

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