W311
Document #: 38-07703 Rev. **
Page 17 of 19
REF Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
––
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
–40
–
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
––
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
–40
–
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
fD
Deviation from 24 MHz
(24.004 – 24)/24
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
––
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
–40
–a
Ω
Ordering Information
Ordering Code
Package Type
Product Flow
W311H
48-pin SSOP
Commercial, 0°C to 70°C
W311HT
48-pin SSOP - Tape and Reel
Commercial, 0°C to 70°C
Lead-free
CYW311OXC
48-pin SSOP
Commercial, 0°C to 70°C
CYW311OXCT
48-pin SSOP - Tape and Reel
Commercial, 0°C to 70°C
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