Introduction to RS08

Getting Started with RS08, Rev. 1

Freescale Semiconductor

21

bra

InfLoop

ACMP_ISR:

;... <ISR coding> ...

bra

InfLoop

KBI_ISR:

;... <ISR coding> ...

bra

InfLoop

RTI_ISR:

;... <ISR coding> ...

bra

InfLoop

LVD_ISR:

;... <ISR coding> ...

bra

InfLoop

The above example illustrates the software priority handling technique. In the example the MCU enters

wait mode during the application idle state. RS08 CPU requires typically three bus cycles to wakeup from

wait mode, the interrupt latency is mainly due to the software execution time. Assuming a bus frequency

of 10MHz (bus period is 100ns) the corresponding latencies are summarized in Table 1-6. User is free to

customize the software loop and minimize the interrupt latency according to the application requirement.

NOTE

In the above example COP is refreshed before entering wait mode. In order

to avoid a COP reset, at least one interrupt event is expected within the COP

timeout period.

In many applications the interrupt period is much longer, it would be wise to put the MCU in stop mode

to minimize the power consumption, particularly in battery operated applications. Because the RS08 CPU

can only be waked up from stop by asynchronous interrupt source such as KBI, ACMP, etc., all

synchronous interrupt events checking such as MTIM can be eliminated from the interrupt servicing loop.

For MC9RS08KA2, all interrupt sources except MTIM has stop wakeup capability (refer to

MC9RS08KA2 data sheet for more details). On top of the software execution time the interrupt latency

from stop must include the MCU stop recovery time that allows the system clock and internal regulator to

wakeup from their standby mode. The stop recovery time varies among product families, it depends on the

clock module and internal regulator technology used.

Table 1-6. Interrupt Latency based on 10MHz Bus Clock

Interrupt

Latency (

µs)

MTIM

0.8

ACMP

1.3 1

NOTES:

1 Additional delay (typically 2 bus clock cycles) may exist to synchronize

the asynchronous interrupt source to the bus clock.

KBI

1.8 1

RTI

2.3 1

LVD

2.8 1