DAC7564 datasheet(27/46 Pages) TI

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SERIAL INTERFACE

IOVDD AND VOLTAGE TRANSLATORS

INPUT SHIFT REGISTER

DAC7564

SBAS413A – FEBRUARY 2008 – REVISED MARCH 2008

falling edge of SCLK is received, the SYNC line may

be kept LOW or brought HIGH. In either case, the

The DAC7564 has a 3-wire serial interface (SYNC,

minimum delay time from the 24th falling SCLK edge

SCLK, and DIN) compatible with SPI, QSPI, and

to the next falling SYNC edge must be met in order to

Microwire interface standards, as well as most DSPs.

properly begin the next cycle. To assure the lowest

See the Serial Write Operation timing diagram for an

power consumption of the device, care should be

example of a typical write sequence.

taken that the levels are as close to each rail as

possible. Refer to the Typical Characteristics section

The DAC7564 input shift register is 24 bits wide,

for Figure 36, Figure 57, and Figure 79 (Supply

consisting of eight control bits (DB23 to DB16) and 12

Current vs Logic Input Voltage).

data bits (DB15 to DB4). Bits DB0, DB1, DB2, and

DB3 are ignored by the DAC and should be treated

as don't care bits. All 24 bits of data are loaded into

the DAC under the control of the serial clock input,

The IOVDD pin powers the digital input structures of

SCLK. DB23 (MSB) is the first bit that is loaded into

the DAC7564. For single-supply operation, it can be

the DAC shift register, and is followed by the rest of

tied to AVDD. For dual-supply operation, the IOVDD pin

the

24-bit

word

pattern,

left-aligned.

This

provides interface flexibility with various CMOS logic

configuration means that the first 24 bits of data are

families and should be connected to the logic supply

latched into the shift register and any further clocking

of the system. Analog circuits and internal logic of the

of data is ignored. The DAC7564 receives all 24 bits

DAC7564 use AVDD as the supply voltage. The

of data and decodes the first eight bits in order to

external logic high inputs translate to AVDD by level

determine the DAC operating/control mode. The 12

shifters. These level shifters use the IOVDD voltage as

bits of data that follow are decoded by the DAC to

a reference to shift the incoming logic HIGH levels to

determine the equivalent analog output, while the last

AVDD. IOVDD is ensured to operate from 2.7V to 5.5V

four bits (DB3, DB2, DB1, and DB0) are ignored. The

regardless of the AVDD voltage, assuring compatibility

data

format

straight

binary

with

all

'0's

with various logic families. Although specified down to

corresponding to 0V output and all '1's corresponding

2.7V, IOVDD operates at as low as 1.8V with

to full-scale output (that is, VREF – 1 LSB). For all

degraded timing and temperature performance. For

documentation

purposes,

the

data

format

and

lowest power consumption, logic VIH levels should be

representation used here is a true 12-bit pattern (that

as close as possible to IOVDD, and logic VIL levels

is, 0FFFh for full-scale), even if the usable 12 bits of

should be as close as possible to GND voltages.

data are extracted from a left-justified, 16-bit data

format that the DAC7564 requires.

The write sequence begins by bringing the SYNC line

The input shift register (SR) of the DAC7564 is 24

low. Data from the DIN line are clocked into the 24-bit

bits wide, as shown in Table 4, and consists of eight

shift register on each falling edge of SCLK. The serial

control bits (DB23 to DB16), 12 data bits (DB15 to

clock frequency can be as high as 50MHz, making

DB4), and four don't care bits. The first two control

the DAC7564 compatible with high-speed DSPs. On

bits (DB23 and DB22) are the address match bits.

the 24th falling edge of the serial clock, the last data

The DAC7564 offers hardware-enabled addressing

bit is clocked into the shift register and the shift

capability, allowing a single host to talk to up to four

DAC7564s through a single SPI bus without any glue

shift register data. After 24 bits are locked into the

logic, enabling up to 16-channel operation. The state

shift register, the eight MSBs are used as control bits

of DB23 should match the state of pin A1; similarly,

and the following 12 LSBs are used as data. After

the state of DB22 should match the state of pin A0. If

receiving the 24th falling clock edge, the DAC7564

there is no match, the control command and the data

decodes the eight control bits and 12 data bits to

(DB21...DB0) are ignored by the DAC7564. That is, if

perform the required function, without waiting for a

there is no match, the DAC7564 is not addressed.

SYNC rising edge. A new write sequence starts at the

Address

matching

can

overridden

the

next falling edge of SYNC. A rising edge of SYNC

broadcast update.

before the 24-bit sequence is complete resets the SPI

interface; no data transfer occurs. After the 24th

Table 4. Data Input Register Format

DB23

DB12

LD1

LD0

DAC Select 1

DAC Select 0

PD0

D11

D10

DB11

DB0

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