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28F800C3 Datasheet(PDF) 19 Page - Numonyx B.V

Part # 28F800C3
Description  Advanced Boot Block Flash
PDF  70 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

28F800C3 Datasheet(HTML) 19 Page - Numonyx B.V

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March 2008
Datasheet
290645-24
19
C3 Discrete
4.2
64-Ball Easy BGA Package
Figure 8: 64-Ball Easy BGA Package1,2
Notes:
1.
A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
2.
Unused address balls are not populated.
4.3
Signal Descriptions
Table 5:
Signal Descriptions
Symbol
Type
Description
A[MAX:0]
Input
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
DQ[15:0]
Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
CE#
Input
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
to standby levels.
OE#
Input
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
Read operation.
RP#
Input
RESET/DEEP POWER-DOWN: Active-low input.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
Top View- Ball Side
Bottom View - Ball Side
A
1
A
6
A
18
V
PP
V
CC
GND A
10
A
15
A
2
A
17
A
19
(1)
RP# DU A
20
(1)
A
11
A
14
A
3
A
7
WP# WE# DU A
21
(1)
A
12
A
13
A
4
A
5
DU
DQ
8
DQ
1
DQ
9
DQ
3
DQ
12
DQ
6
DU
DU
CE# DQ
0
DQ
10 DQ11
DQ
5
DQ
14
DU
DU
A
0
V
SSQ
DQ
2
DQ
4
DQ
13 DQ15 VSSQ
A
16
A
22
(2) OE# V
CCQ
V
CC
V
SSQ
DQ
7
V
CCQ
DU
DU
DU
DU
A
8
A
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
A
15
A
10
GND V
CC
V
PP
A
18
A
6
A
1
A
14
A
11
A
20
(1)
DU RP# A
19
(1)
A
17
A
2
A
13
A
12
A
21
(1)
DU WE# WP# A
7
A
3
A
9
A
8
DU
DU
DU DQ
6
DQ
12
DQ
3
DQ
9
DQ
1
DQ
8
DU
DU DQ
14
DQ
5
DQ
11 DQ10
DQ
0
CE#
A
16
VSSQ D
15
D
13
DQ
4
DQ
2
V
SSQ
A
0
DU V
CCQ
D
7
V
SSQ
V
CC
V
CCQ
OE# A
22
(2)
DU
DU
DU
A
5
A
4



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