LX1996

Microsemi

Analog Mixed Signal Group

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 13

Copyright

© 2007

Rev. 1.0, 2007-12-14

Multi-string LED Back-light Controller

TM

®

OPERATION THEORY

The internal dimming oscillator can be synchronized to an

external clock on the PWM input. A PLL loop filter capacitor

must be connected between CLF and GND pins for

synchronization. Use 0.1uF for 200Hz, 0.001uF for 20KHz.

The RT, CT and CLF pins can be left open if both the internal

dimming and ultrasonic pulse skipping modes are not used.

In this mode, a DC voltage on the DI pin is used to vary the

reference voltage at the PRG pin. The PRG pin reference

voltage, in conjunction with the resistor connected between the

PRG pin and ground, sets the LED current. The ratio of DI

input voltage to PRG pin voltage is 1:1, up to 2V input. The DI

input voltage range is 0V to 5V, however, the voltage at PRG

pin is limited to 0.2V to 2V with an internal voltage clamp.

Thus the dimming ratio is limited to 10:1. A higher dimming

ratio is obtained in the Combined Analog and Digital Dimming

mode.

The table below summarizes the dimming modes.

Table 1 - Dimming Modes

DSEL1

DSEL2

Dimming Method

Low

Low

Direct Digital Dimming

Low

Hi

Combined Analog and

Digital Dimming Modes

Hi

Low

Direct Analog Dimming

Hi

Hi

Direct Analog Dimming

with Ultrasonic Pulse

Skipping (USPS)

Open

Low

Analog to Digital dimming

with internal clock

Open

Hi

Analog to Digital dimming

with external clock

synchronization.