AT25SF641B datasheet(28/62 Pages) RENESAS

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DS-AT25SF641B-191 Rev. K

Page 28

2025-12-12

AT25SF641B Datasheet

8.4

Chip Erase (60h or C7h)

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip

Erase command can be started, the Write Enable command must have been previously issued to the device to set

the WEL bit of the Status Register to a logical 1 state.

Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device

functionality when using the two opcodes; thus, they can be used interchangeably. To perform a Chip Erase, one

of the two opcodes must be clocked into the device. Since the entire memory array is to be erased, no address

bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS pin is

deasserted, the device erases the entire memory array. The erasing of the device is internally self-timed and takes

place in a time of tCHPE.

The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on an byte boundary (multiples of eight bits); otherwise, no erase is performed. Also, if the memory

array is in the protected state, the Chip Erase command is not executed, and the device returns to the idle state

once the CS pin has been deasserted. The WEL bit in the Status Register is reset to the logical 0 state if the CS

pin is deasserted on uneven byte boundaries, or if the memory is in the protected state.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled to determine if the

device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register is

reset to the logical 0 state.

Figure 21. Chip Erase Timing

SCK

MSB

CCCCCCCC

OPCODE

HIGH-IMPEDANCE

Mode 3

Mode 0

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