APEX20KC datasheet(26/90 Pages) ALTERA

26 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 14. APEX 20KC Macrocell

For registered functions, each macrocell register can be programmed

individually to implement D, T, JK, or SR operation with programmable

clock control. The register can be bypassed for combinatorial operation.

During design entry, the designer specifies the desired register type; the

Quartus II software then selects the most efficient register operation for

each registered function to optimize resource utilization. The Quartus II

software or other synthesis tools can also select the most efficient register

operation automatically when synthesizing HDL designs.

Each programmable register can be clocked by one of two ESB-wide

clocks. The ESB-wide clocks can be generated from device dedicated clock

pins, global signals, or local interconnect. Each clock also has an

associated clock enable, generated from the local interconnect. The clock

and clock enable signals are related for a particular ESB; any macrocell

using a clock also uses the associated clock enable.

If both the rising and falling edges of a clock are used in an ESB, both

ESB-wide clock signals are used.

Clock/

Enable

Select

Product-

Term

Select

Matrix

Parallel Logic

Expanders

(From Other

Macrocells)

ESB-Wide

Clears

ESB-Wide

Clock Enables

ESB-Wide

Clocks

32 Signals

from Local

Interconnect

Clear

Select

ESB

Output

Programmable

222

ENA

CLRN

APEX20KC Datasheet(PDF) 26 Page - Altera Corporation

APEX20KC Datasheet(HTML) 26 Page - Altera Corporation

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