APEX20KC datasheet(42/90 Pages) ALTERA

42 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 27 shows how a column IOE connects to the interconnect.

Figure 27. Column IOE Connection to the Interconnect

Dedicated Fast I/O Pins

APEX 20KC devices incorporate an enhancement to support bidirectional

pins with high internal fan-out such as PCI control signals. These pins are

called dedicated fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and

replace dedicated inputs. These pins can be used for fast clock, clear, or

high fan-out logic signal distribution. They also can drive out. The

dedicated fast I/O pin data output and tri-state control are driven by local

interconnect from the adjacent MegaLAB for high speed.

Row Interconnect

Column Interconnect

Each IOE can drive a column interconnect. IOEs can also

drive FastRow and column interconnects. Each IOE data

and OE signal is driven by local interconnect.

Any LE or ESB can drive

a column pin through a

row, column, and MegaLAB

interconnect.

IOE

LAB

An LE or ESB can drive a

pin through a local

interconnect for faster

clock-to-output times.

MegaLAB Interconnect

APEX20KC Datasheet(PDF) 42 Page - Altera Corporation