TMS320DM641 datasheet(168/179 Pages) TI

168 / 179 page

JTAG

168

June 2003 − Revised October 2005

SPRS222E

4.19 JTAG

The JTAG interface is used for BSDL testing and emulation of the DM641/DM640 device.

4.19.1

JTAG Device-Specific Information

4.19.1.1 IEEE 1149.1 JTAG Compatibility Statement

The TMS320DM641/DM640 DSP requires that both TRST and RESET be asserted upon power up to be

properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both

resets are required for proper operation.

Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected

after TRST is asserted.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the

DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface

and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a

JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be

released in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan

instructions work correctly independent of current state of RESET.

The TMS320DM641/DM640 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST

will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized

when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However,

some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor

on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and

externally drive TRST high before attempting any emulation or boundary scan operations.

Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and

EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.

For more detailed information, see the terminal functions section of this data sheet.

Note: The DESIGN_WARNING section of the TMS320DM641/DM640 BSDL file contains information and

constraints regarding proper device operation while in Boundary Scan Mode.

For more detailed information on the DM641 and DM640 JTAG emulation, see the TMS320C6000 DSP

Designing for JTAG Emulation Reference Guide (literature number SPRU641).

4.19.1.2 JTAG ID Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

DM641/DM640 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value

for the DM641/DM640 device is: 0x0007 902F. For the actual register bit names and their associated bit field

descriptions, see Figure 4−66 and Table 4−82.

31−28

27−12

11−1

VARIANT (4-Bit)

PART NUMBER (16-Bit)

MANUFACTURER (11-Bit)

LSB

R-0000

R-0000 0000 0111 1001

R-0000 0010 111

R-1

Legend: R = Read only; -n = value after reset

Figure 4−66. JTAG ID Register Description − TMS320DM641/DM640 Register Value − 0x0007 902F

TMS320DM641 Datasheet(PDF) 168 Page - Texas Instruments

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