CE6313

Data Sheet

15

Intel Corporation

demodulation. Hence a frequency offset will not necessarily lead to a performance loss. Performance loss will occur

only if a significant part of the signal is cut off by the base-band filter, due to this frequency offset. This will happen

only if the symbol rate is close to the maximum supported by that filter. In such an event it is recommended that

front-end be re-tuned to neutralise this error before the filter. It is then necessary for the CE6313 to re-acquire the

signal.

The CE6313 can generate control signals to enable full control of the dish and LNB. The chip implements the

signals needed for the full DiSEqC specification. This includes high/low band selection, polarization and dish

position. In this mode, the symbol rate in MSps and Viterbi code rate are the only values needed to start the

CE6313 searching for the signal. The CDC module maps the high level parameters into the various low level

register settings needed to acquire and track the signal. The low level registers may be read and directly modified

to suit very specific requirements. However, this is not recommended.

Figure 13 - CE6313 Control Structure

2.5.1

Symbol Rate and Code Rate Search Mode

Where the symbol rate and/or the Viterbi code rate are unknown, the CE6313 can be programmed to search for

QPSK/BPSK signals. The user should define the range(s) over which the search is required. The CE6313 will then

locate and track any signal detected. Failure to find a QPSK signal in the specified frequency and specified symbol

rate ranges will be indicated by interrupts. CE6313 will carry on searching these ranges after issuing these

interrupts. When the CE6313 has locked onto a signal, the symbol rate in MSps may be read from the MONITOR

registers. The Viterbi code rate may be read from the FEC_STATUS register. This search facility is primarily for use

during the initial installation of a receiver.

2.6

DiSEqC Transmit and Receive Messages

The CE6313 has the capability to send and receive DiSEqC messages. Eight registers are provided to store a

message for transmission and a further eight registers are provided to store a received message. The received

bytes have a parity bit and a parity error bit in addition to the eight data bits. These additional bits are read out in

sequence following the data bits, so two byte reads are required for each data byte.

2.6.1

DiSEqC Transmitting Messages

The sequence of events to send a message are as follows:

1. Load the required message bytes into the DiSEqC instruction register. Sequential writes to the same register are

achieved by setting the Inhibit Auto Incrementing (IAI) bit 7 in RADD, the register address byte.

2. Load the number of bytes (less one) in the DiSEqC instruction in the register DiS_Mode[5:3].

Command

Driven

Control

CE6313

format

registers

Acquisition/

Track

State Machine

QPSK

Low level register read/write

High level input/output

(MSps, MHz)