PCF85263ATLSLASHAX datasheet(34/92 Pages) NXP

34 / 92 page

NXP Semiconductors

PCF85263A

Tiny Real-Time Clock/calendar with alarm function, battery switch-over, time stamp input, and I2C-bus

7.8.4 Offset interrupts

The generation of interrupts from the offset functions is controlled via the offset interrupt

enable bits; OIEA and OIEB. These bits are in registers INTA_enable (address 29h) and

INTB_enable (address 2Ah).

Every time a correction pulse is made an interrupt pulse can be generated at pins INTA

and INTB. As there is no offset calibration flag, it is only possible to generate pulse

interrupts.

See Section 7.9 for interrupt control.

7.9 Interrupts

There are two interrupt output pins, INTA and INTB. Both pins have the same possible

sources and a dedicated register to control what is output. The pins can be used

independently from each other.

INTA data is output on the INTA pin. INTA is an interrupt output pin with open-drain drive.

INTA pin mode is controlled by INTAPM[1:0] bits in the Pin_IO register (Section 7.12).

INTB data is output on TS pin with push-pull drive. The TS pin must first be configured as

INTB output by setting TSIO[1:0] bits in the Pin_IO register (Section 7.12).

Interrupts will only be output when the pin mode is correctly defined. Interrupts are output

from the IC as active LOW signals.

The registers INTA_enable (address 29h) and INTB_enable (address 2Ah) are used to

select which interrupts should be output on which pin.

Bit

INTA_enable - INTA pin enable control (address 29h)

Symbol

ILPA

PIEA

OIEA

A1IEA

A2IEA

TSRIEA

BSIEA

WDIEA

INTB_enable - INTB pin enable control (address 2Ah)

Symbol

ILPB

PIEB

OIEB

A1IEB

A2IEB

TSRIEB

BSIEB

WDIEB

Table 27. INTA and INTB interrupt control bits

Symbol

Bit

INTA

INTB

Value

Description

level or pulse mode

0 [1]

interrupt generates a pulse

ILPA

ILPB

interrupt follows flags (permanent signal)

periodic interrupt enable

0 [1]

no periodic interrupt generated

PIEA

PIEB

periodic interrupt generated

offset correction interrupt enable

0 [1]

no correction interrupt generated

OIEA

OIEB

interrupt generated from correction

Table 28. Definition of interrupt control bits

PCF85263A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 1 February 2021

34 / 92

PCF85263ATL/AX Datasheet(PDF) 34 Page - NXP Semiconductors

PCF85263ATL/AX Datasheet(HTML) 34 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL