SST29EE010 datasheet(3/26 Pages) SST

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1 Megabit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Write Operation Status Detection

The SST29EE010/29LE010/29VE010 provide two soft-

ware means to detect the completion of a Write cycle, in

order to optimize the system write cycle time. The

software detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The end of write detection

mode is enabled after the rising WE# or CE# whichever

occurs first, which initiates the internal write cycle.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data#

Polling or Toggle Bit read may be simultaneous with the

completion of the Write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7 or DQ6. In order to

prevent spurious rejection, if an erroneous result occurs,

the software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST29EE010/29LE010/29VE010 are in the

internal write cycle, any attempt to read DQ7 of the last

byte loaded during the byte-load cycle will receive the

complement of the true data. Once the Write cycle is

completed, DQ7 will show true data. The device is then

ready for the next operation. See Figure 6 for Data#

Polling timing diagram and Figure 15 for a flowchart.

Toggle Bit (DQ6)

During the internal write cycle, any consecutive attempts

to read DQ6 will produce alternating 0’s and 1’s, i.e.

toggling between 0 and 1. When the Write cycle is

completed, the toggling will stop. The device is then

ready for the next operation. See Figure 7 for Toggle Bit

timing diagram and Figure 15 for a flowchart. The initial

read of the Toggle Bit will typically be a “1”.

Data Protection

The SST29EE010/29LE010/29VE010 provide both

hardware and software features to protect nonvolatile

data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than

5 ns will not initiate a Write cycle.

VCC Power Up/Down Detection: The Write operation is

inhibited when VCC is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inad-

vertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST29EE010/29LE010/29VE010 provide the

JEDEC approved optional Software Data Protection

scheme for all data alteration operations, i.e., Write and

Chip-Erase. With this scheme, any Write operation re-

quires the inclusion of a series of three byte-load opera-

tions to precede the data loading operation. The three

byte-load sequence is used to initiate the Write cycle,

providing optimal protection from inadvertent write opera-

tions, e.g., during the system power-up or power-down.

The SST29EE010/29LE010/29VE010 are shipped with

the Software Data Protection disabled.

The software protection scheme can be enabled by

applying a three-byte sequence to the device, during a

page-load cycle (Figures 4 and 5). The device will then

be automatically set into the data protect mode. Any

subsequent Write operation will require the preceding

three-byte sequence. See Table 4 for the specific soft-

ware command codes and Figures 4 and 5 for the timing

diagrams. To set the device into the unprotected mode,

a six-byte sequence is required. See Table 4 for the

specific codes and Figure 8 for the timing diagram. If a

write is attempted while SDP is enabled the device will be

in a non-accessible state for ~ 300 µs. SST recommends

Software Data Protection always be enabled. See Figure

16 for flowcharts.

The SST29EE010/29LE010/29VE010 Software Data

Protection is a global command, protecting

(or unprotecting) all pages in the entire memory array

once enabled (or disabled). Therefore using SDP for a

single Page-Write will enable SDP for the entire array.

Single pages by themselves cannot be SDP enabled or

disabled.

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