RC22504A datasheet(39/81 Pages) RENESAS

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RC22504A Datasheet

R31DS0043EU0112 Rev.1.12

Aug 1, 2025

Page 39

When reading, a configurable number of dummy bytes can be read before the requested data byte(s) as

controlled by the spi_dummy_en and spi_dummy_size register fields. When the SPI clock is faster than the

system clock frequency divided by 4, at least 1 dummy byte must be enabled. Writes do not use dummy bytes.

Figure 17. SPI Sequencing

Figure 17 shows the sequencing of address and data on the serial port. The R/W bit is high for read cycles and

low for write cycles. The read sequence is shown without dummy bytes (spi_dummy_en set to 0). If 1 dummy byte

were enabled, then the data bits labeled Data byte from Address provided would be zero, the data bits labeled

Data byte from Address + 1 would become Data byte from Address provided, and they would be followed by

another 8 bits containing Data byte from Address + 1.

SPI operation can be configured for the following settings through register fields:

• 1-byte (1B) or 2-byte (2B) offset addressing (ssi_addr_size) (see Figure 15)

• In 1B operation, the 16-bit register address is formed by using the 7 bits of address supplied in the SPI access

and taking the upper 9 bits from the page register. The page register is accessed using an Offset Address of

0x7C with a 4-byte burst access.

• In 2B operation, the 16-bit register address is formed by using the 15 bits of address supplied in the SPI access

and the upper 1-bit is fixed to b’0.

• Data sampling on falling or rising edge of SCLK (spi_clk_sel)

• Output (read) data positioning relative to active SCLK edge (spi_del_out)

Note: SPI burst mode operation is recommended to ensure data integrity of multi-byte registers. When accessing

a multi-byte register, all data bytes must be written or read in a single SPI burst access. Bursts can be of greater

length if desired but must not extend beyond the end of the register page. An internal address pointer is

incremented automatically as each data byte is written or read.

SPI timing is shown in Figure 4 and Table 17.

The SPI interface operating at 20MHz supports a DCO update rate of approximately 400k updates per second.

A14

A13

A12

A11

A10

R/W

nCS

SCLK

SDI

(4-wire)

SDO

(4-wire)

A10

A11

A12

A13

A14

R/W

nCS

SCLK

SDI

(4-wire)

SDO

(4-wire)

Hi-Z

SPI Read Sequence*

SPI Write Sequence*

XX (SDI unused while data being read)

A14-A7 are omitted in 7b SPI Addressing Mode

Data byte from Address provided

Data byte from Address + 1

A14

A13

A12

A11

A10

R/W

A14-A7 are omitted in 7b SPI Addressing Mode

Data byte to Address provided

Data byte to Address + 1

A10

A11

A12

A13

A14

R/W

SDIO

(3-wire)

A14

A13

A12

A11

A10

R/W

A10

A11

A12

A13

R/W

SDIO

(3-wire)

A14

A13

A12

A11

A10

R/W

SDIO Driven by Master

SDIO Driven by Slave

SDIO Driven by Master

* See the timing diagrams for exact timing relationships.

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