RC22504A datasheet(13/81 Pages) RENESAS

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RC22504A Datasheet

R31DS0043EU0112 Rev.1.12

Aug 1, 2025

Page 13

3.3 Reference Clock Phase Jitter and Phase Noise

Figure 2. 156.25MHz Output Phase Noise - Integer Synthesizer Mode

Table 6. Output Phase Jitter Characteristics[1][2]

[1] VDDXO = VDDA = VDDOx = 1.8V ±5%, GND = 0V, TA = -40°C to 85°C.

[2] Electrical parameters are ensured over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device meets specifications after

thermal equilibrium has been reached under these conditions.

Symbol

Parameter

Test Condition

Typical

Maximum

Unit

tjit()

Phase Jitter, RMS (Random)[3]

[3] Characterized using a Rohde and Schwarz SMA100A overdriving the XTAL Interface.

10kHz to 20MHz

78.125MHz

Crystal[4];

Synthesizer

Mode

[4] APLL at 10.625GHz to allow for outputting common ETH/FC frequencies.

106.25MHz

100

125MHz

100

156.25MHz

100

212.5MHz

100

312.5MHz

100

tjit()

Phase Jitter, RMS (Random)[5]

[5] Characterized using a Rohde and Schwarz SMA100A overdriving the XTAL Interface.

10kHz to 20MHz

156.25MHz

Input[6];

Clock Generator

Mode

[6] Driven by output from ClockMatrix. APLL at 10GHz to allow for outputting common ETH frequencies.

125MHz

100

156.25MHz

100

312.5MHz

100

SSB(100k)

Single Sideband

Phase Noise

100kHz

156.25MHz input,

Clock Generator Mode;

All outputs enabled at 156.25MHz

-148

dBc/Hz

SSB(1M)

1MHz

-153

dBc/Hz

SSB(10M)

10MHz

-165

dBc/Hz

SSB(30M)

≥30MHz

-167

dBc/Hz

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