RC22504A datasheet(21/81 Pages) RENESAS

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RC22504A Datasheet

R31DS0043EU0112 Rev.1.12

Aug 1, 2025

Page 21

Figure 4. SPI Timing Diagram

Table 17. SPI Slave Timing

Parameter

Description

Minimum

Typical

Maximum

Unit

fMAX

Maximum operating frequency

MHz

tPWH

SCLK Pulse Width High

tPWL

SCLK Pulse Width Low

tSU1

nCS Setup Time to SCLK rising or falling edge

tHD1

nCS Hold Time from SCLK rising or falling edge

tSU2

SDIO Setup Time to SCLK rising or falling edge

tHD2

SDIO Hold Time from SCLK rising or falling edge

tD1

Read Data Valid Time from SCLK rising or falling edge with

no data delay added

5.6

tD1d

Read Data Valid Time from SCLK rising or falling edge

including half period of SCLK delay added to data timing[1]

[1] Adding the extra half period of delay is a register programming option to emulate read data being clocked out on the opposite edge

of the SCLK to the write data.

tD1 + half

SCLK period

tD2

SDIO Read Data Hi-Z Time from CS High[2]

[2] This is the time until the RC22504A releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength

and PCB trace loading.

nCS

SCLK

SDI

SDIO (SPI_SDO_DELAY = 0)

Hi-Z

spi_clk_sel = 0

nCS

SCLK

SDI

R/W

A(n)

A(n-1)

R/W

A(n)

A(n-1)

Write D(n)

Hi-Z

Read D(n)

Hi-Z

Read D(n)

A(0)

SDIO (SPI_SDO_DELAY = 1)

Write D(n-1)

spi_clk_sel = 1

SDIO (SPI_SDO_DELAY = 0)

SDIO (SPI_SDO_DELAY = 1)

A(0)

Write D(n-1)

Read D(0)

Write D(0)

Read D(0)

Wr D(0)

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