RC32504A datasheet(39/100 Pages) RENESAS

39 / 100 page

RC32504A Datasheet

R31DS0044EU0113 Rev.1.13

Aug 1, 2025

Page 39

The automatic reference selection can either be revertive or non-revertive which is set in register

dpll_revertive_en. In revertive mode, the reference clock that is qualified and of the highest priority is always

selected. In non-revertive mode, if there is a higher priority reference clock coming back from disqualified to

qualified, the current selected reference clock remains selected unless it gets disqualified.

6.6.3.3

Hitless Reference Switching

If hitless switching is enabled by setting register dpll_hitless_en to ‘1’, the output clock initial phase hit is

minimized (<200ps) during reference switching or the DPLL exiting from holdover, while the input clock and output

clock may no longer be aligned.

If hitless is disabled, the output clock phase change slope is determined by DPLL loop characteristics and phase

slope limit settings in register phase_slope_limit.

Hitless (<200ps) only can be met when the reference clocks are of same fractional frequency offset. If they are of

different fractional frequency offset (up to ±244ppm), the output clock phase tracks to the new reference clock.

Although the initial phase hit could be minimized by setting dpll_hitless_en to ‘1’, the total amount of output phase

change and the change slope depends on the fractional frequency offset difference, the loop characteristics, and

phase slope limit settings.

When dpll_hitless_en is set to one and enabled, the phase_offset register is ignored by the DPLL and only the

internally stored hitless offset affects the input-output phase offset. When dpll_hitless_en is set to zero and

disabled, the hitless phase offset stored in the hitless handler is reset to zero and the phase_offset register is

used again. Hitless switching minimizes the output phase movement at the expense of a defined input-output

phase offset while the use of the phase offset register enables a defined input-output phase offset at the expense

of output phase movement during reference switching. Defined input-output phase offset and minimizing output

phase movement are mutually exclusive.

6.6.4

Digital Loop Filter

The digital loop filter is a Proportional - Integrator (PI) type filter as shown in Figure 17. It is programmable to a

bandwidth of approximately 0.1Hz to 12kHz.

Figure 17. Loop Filter Block Diagram

The phase corrections are mainly done through the proportional path while the frequency offset is done in the

integrator. The phase input can come from the phase detector/decimator and an offset from CSR. The phase

value gets multiplied by a bandwidth factor. These are programmed in the normal_bw_mult and normal_bw_shift

reg

Write_freq from CSR

Phase from

decimator

phase offset

from CSR

bandwidth

damping

prop_int_term

Freq Offset

limiter

integrator

Prop(ortional)-term

shift

int_term

shift

Proportional_enable

Integrator _enable

integrator_mode

RC32504A Datasheet(PDF) 39 Page - Renesas Technology Corp

RC32504A Datasheet(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL