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RC32504A Datasheet(PDF) 13 Page - Renesas Technology Corp

Part # RC32504A
Description  FemtoClock®2 Sub-100fs Universal Frequency Translator
PDF  100 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RC32504A Datasheet(HTML) 13 Page - Renesas Technology Corp

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RC32504A Datasheet
R31DS0044EU0113 Rev.1.13
Aug 1, 2025
Page 13
3.3 Reference Clock Phase Jitter and Phase Noise
Table 6. Output Phase Jitter Characteristics[1][2]
[1] VDDXO = VDDA = VDDOx = 1.8V ±5%, GND = 0V, TA = -40°C to 85°C.
[2] Electrical parameters are ensured over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device meets specifications after
thermal equilibrium has been reached under these conditions.
Symbol
Parameter
Test Condition
Typical
Maximum
Unit
tjit()
Phase Jitter, RMS (Random)[3]
[3] Characterized using a Rohde and Schwarz SMA100A overdriving the XTAL Interface.
10kHz to 20MHz
78.125MHz
Crystal[4];
Synthesizer
Mode
[4] APLL at 10.625GHz to allow for outputting common ETH/FC frequencies.
106.25MHz
78
100
fs
125MHz
73
100
fs
156.25MHz
72
100
fs
212.5MHz
71
100
fs
312.5MHz
67
100
fs
tjit()
Phase Jitter, RMS (Random)[5]
[5] Characterized using a Rohde and Schwarz SMA100A overdriving the XTAL Interface.
10kHz to 20MHz
60MHz
Crystal[6];
JA Mode Locked
to 25MHz CLKIN
[6] APLL at 9.8304GHz for 245.76MHz, 491.52MHz and 983.04MHz. APLL at 10.3125GHz for 156.25MHz, 312.5MHz, and
322.265625MHz.
156.25MHz
105
130
fs
245.76MHz
104
130
fs
312.5MHz
101
130
fs
322.265625MHz
104
130
fs
491.52MHz
102
130
fs
983.04MHz
101
130
fs
tjit()
Phase Jitter, RMS (Random)[7]
[7] Characterized using a Rohde and Schwarz SMA100A overdriving the XTAL Interface.
10kHz to 20MHz
156.25MHz
Input[8];
Clock Generator
Mode
[8] Driven by output from ClockMatrix. APLL at 10GHz to allow for outputting common ETH frequencies.
125MHz
74
100
fs
156.25MHz
73
100
fs
312.5MHz
64
100
fs
SSB(100k)
Single Sideband
Phase Noise
100kHz
156.25MHz input,
Clock Generator Mode;
All outputs enabled at 156.25MHz
-148
-
dBc/Hz
SSB(1M)
1MHz
-153
-
dBc/Hz
SSB(10M)
10MHz
-165
-
dBc/Hz
SSB(30M)
≥30MHz
-167
-
dBc/Hz
SSB(100)
Single Sideband
Phase Noise
100Hz
60MHz Crystal,
JA Mode with 25Hz loop bandwidth,
25MHz input from SMA-100;
All outputs enabled at 156.25MHz
-103
-
dBc/Hz
SSB(1k)
1kHz
-113
-
dBc/Hz
SSB(10k)
10kHz
-132
-
dBc/Hz
SSB(100k)
100kHz
-140
-
dBc/Hz
SSB(1M)
1MHz
-154
-
dBc/Hz
SSB(10M)
10MHz
-164
-
dBc/Hz
SSB(30M)
≥30MHz
-166
-
dBc/Hz



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