RC32504A datasheet(21/100 Pages) RENESAS

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RC32504A Datasheet

R31DS0044EU0113 Rev.1.13

Aug 1, 2025

Page 21

Figure 4. I2C Slave Timing Diagram

[8] Refers to the output voltage (swing) setting programed into device registers for each output using the ODRV_AMP_CNFG

[9] Refers to the output voltage (amplitude) setting programed into device registers for each output using the ODRV_AMP_CNFG

Table 14. LVCMOS Status and Control Signal DC Characteristics[1][2][3]

[1] 3.3V characteristics in accordance with JESD8C-01, 1.8V characteristics in accordance with JESD8-7A.

[2] GND = 0V, TA = -40°C to 85°C.

[3] Input specifications see signals SCL_SCLK, SDA_SDIO, OE_nCS. Output specifications see signals LOCK, SDA_SDIO (3-wire

SPI).

Symbol

Parameter

Test Condition

Minimum

Typical

Maximum

Unit

VIH

Input High Voltage

VDDD = 3.3V ±5%

VDDD + 0.3

VDDD = 1.8V ±5%

0.65 × VDDD

VDDD + 0.3

VIL

Input Low Voltage

VDDD = 3.3V ±5%

-0.3

0.8

VDDD = 1.8V ±5%

-0.3

0.35 × VDDD

IIH

Input High Current

VIN = VDDD = VDDD (max)

µA

IIL

Input Low Current

VIN = 0V,

VDDD = VDDD (max)

-75

µA

VOH

Output High Voltage

VDDD = 3.3V ±5% or 1.8V ±5%

IOH = -100µA

VDDD - 0.2

(LOCK Signal Only)

VDDA = 1.8V ±5%

IOH = -100µA

VDDA - 0.2

VOL

Output Low Voltage

VDDD = 3.3V ±5% or 1.8V ±5%

VDDA = 1.8V ±5%

IOL = 100µA

0.2

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:STA

tSU:STO

tBUF

SCL

SDA

MSB

tSU:DAT

tHD:DAT

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