R31DS0136EU0102 Rev.1.02

Page 13

Dec 6, 2024

RC32508A Datasheet

1.11 Output Dividers

The RC32508A provides eight integer output dividers (IOD), and each of the two APLLs feeds into four output

dividers.

1.11.1 Integer Output Dividers

All eight IODs are identical and first four IODs derive the input clock from APLL0, and second four IODs derive the

input clock from APLL1. Each IOD provides output frequencies from 1MHz to 1GHz. Changing IOD values results

in an immediate change to the new frequency. Glitchless squelch and release of the IOD clock is supported.

1.12 Clock Outputs

The RC32508A supports up to 8 differential or 16 single-ended clock outputs or any combination of differential

and single-ended clock outputs. Each differential clock output can be programmed as two single-ended clock

outputs.

1.12.1 Output Buffer in Single-Ended Mode

When used as a single-ended output buffer, two copies of the same output clock are created with LVCMOS output

levels. Each clock will have the same frequency, phase, voltage, and current characteristics.

1.12.2 Output Buffer in Differential Mode

When used as a differential output buffer, the user can control the output voltage swing (VOVS) and common mode

voltage (VCMR) of the buffer that can be DC-coupled to HCSL input interface and AC-coupled to LVDS, LVPECL,

or CML input interfaces.

1.12.3 Output Enable Control

During the power-up sequence, the clock output drivers are powered down (OUTx-0/1 and nOUTx-0/1 are tri-

stated) until the power supplies have stabilized. Then the output drivers are powered up in the default disabled

state (OUTx-0/1 and nOUTx-0/1 are both held low).

After the OTP configuration load completes, the clock output drivers can be held disabled until the APLL and/or

DPLL locks:

▪ Clock output drivers are disabled until APLL lock asserts

▪ Clock output drivers are disabled until DPLL lock asserts

▪ Clock output drivers are enabled immediately

After startup, the clock output drivers are then user-controllable using output enable control.

1.13 OTP

The RC32508A supports four user-definable, non-volatile start-up configurations stored in an internal OTP (one-

time programmable) memory that covers the blocks related to DPLL, APLL0, four output dividers feeding OUT0-0,

OUT1-0, OUT2-0, OUT3-0. An additional four user-definable non-volatile start-up configurations stored in an

internal OTP memory that covers the blocks related to APLL1, four output dividers feeding OUT0-1, OUT1-1,

OUT2-1, OUT3-1. Each configuration can store values for all write-able configuration registers. The configuration

for DPLL, APLL0 and the four outputs fed by APLL0 is selected by the values of LOCK-0, OE_nCS-0, and latched

at power-up. The configuration for APLL1 and the four outputs fed by APLL1 is selected by the values of LOCK-1,

OE_nCS-1 and latched at power-up. The serial interfaces are inactive until all register values specified in the

selected configuration are written. The OTP contents can be locked to prevent further programming. The

RC32508A supports OTP read with a VDDD0/1 supply voltage of 1.8V.