R31DS0136EU0102 Rev.1.02

Page 21

Dec 6, 2024

RC32508A Datasheet

fMON

Reference Monitor

Operating

Frequency

CLKMON0/1

-

-

33

MHz

CLKMON2

-

-

312.5

MHz

tstartup

Start-up Time [3]

Internal OTP

Start-up

Synthesizer mode

-

7

10

ms

1. VDDXO-0, VDDXO-1 = VDDD-0, VDDD-1 = VDDA-0, VDDA-1 = VDDOx-0, VDDOx-1 = 1.8V ±5%, GND = 0V, TA = -40°C to 85°C.

2. Electrical parameters are ensured over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device meets specifications after thermal

equilibrium has been reached under these conditions.

3. Measured from when all power supplies have reached > 80% of nominal voltage to the first stable clock edge on the output. A stable

clock is defined as one generated from a locked analog or digital PLL (as appropriate for the configuration listed) with no further

perturbations in frequency expected.

Table 9. Output Frequency Characteristics [1][2]

Symbol

Parameter

Test Condition

Minimum

Typical

Maximum

Unit

fOUT

Output

Frequency

Differential

Output

10

-

1000

MHz

LVCMOS

Output

10

-

180

MHz

tSK

Output to Output

Skew [3][4]

Differential [5]

Any two outputs between

OUTx-0

-

9

38

ps

Any two outputs between

OUTx-0 and OUTx-1

41

128

ps

LVCMOS [6]

Any two outputs between

OUTx-0

-

30

50

ps

Any two outputs between

OUTx-0 and OUTx-1

-

50

96

ps

ΔtSK

Temperature Variation [7] Output-

Output

On OUTx-0, OUTx-1

-

-

1

ps/°C

tPD

Input to Output Skew [8] Differential

[5] WRT CLKIN [9]

Delay for SYNTH mode on

OUTx-0, OUTx-1

0.73

1.14

1.55

ns

tPD

Input to Output Skew [10]

Differential [5] WRT CLKIN [11]

Delay for JA mode, integer

DPLL feedback on OUTx-0

0.65

1.08

1.52

ns

Delay for JA mode,

fractional DPLL feedback

on OUTx-0

0.72

1.09

1.47

ns

Delay for SYNTH mode on

OUTx-1

0.74

1.14

1.55

ns

ΔtPD

Input to Output Delay Variation

Differential [5]

Any mode on OUTx-0,

OUTx-1

-

-

255

ps

tR / tF

Output Rise and

Fall Times 20%

to 80%

Differential

Output [12]

HCSL Mode

-

-

160

ps

LVDS Mode

-

-

180

ps

LVCMOS

Output [13]

VDDOx =

1.8V ±5%

-

-

800

ps

Table 8. PLL Characteristics [1][2] (Cont.)

Symbol

Parameter

Test Condition

Minimum

Typical

Maximum

Unit