CP8056SS datasheet(13/46 Pages) ETC2

13 / 46 page

CHENGPIN

CP8056

P.13/

CP8056

/PHB7 : = 0, Enable the internal pull-high of IOB7 pin.

= 1, Disable the internal pull-high of IOB7 pin.

2.1.13 INTEN (Interrupt Mask Register)

Address

Name

0Eh (r/w)

INTEN

GIE

INTIE

PBIE

T0IE

T0IE : Timer0 overflow interrupt enable bit.

= 0, Disable the Timer0 overflow interrupt.

= 1, Enable the Timer0 overflow interrupt.

PBIE : Port B input change interrupt enable bit.

= 0, Disable the Port B input change interrupt.

= 1, Enable the Port B input change interrupt .

INTIE : External INT pin interrupt enable bit.

= 0, Disable the External INT pin interrupt.

= 1, Enable the External INT pin interrupt.

Bit6:BIT3 : Not used. Read as “0”s.

GIE : Global interrupt enable bit.

= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue

execution at the instruction after the SLEEP instruction.

= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device

will branch to the interrupt address (008h).

Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the

GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the

interrupt routine and set the GIE bit to re-enable interrupt.

2.1.14 INTFLAG (Interrupt Status Register)

Address

Name

0Fh (r/w)

INTFLAG

INTIF

PBIF

T0IF

T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.

PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software.

INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin,

reset by software.

Bit7:BIT3 : Not used. Read as “0”s.

2.1.15 ACC (Accumulator)

Address

Name

N/A (r/w)

ACC

Accumulator

Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed.

2.1.16 OPTION Register

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