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STA328

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6.3

Configuration register C (addr 0x02)

6.3.1

DDX® power output mode

The DDX® power output mode selects how the DDX® output timing is configured. Different

power devices can use different output modes. The recommended use is OM = 10. When

OM = 11 the CSZ bits determine the size of the DDX® compensating pulse.

6.3.2

DDX® variable compensating pulse size

The DDX® variable compensating pulse size is intended to adapt to different power stage

ICs. Contact Apogee applications for support when deciding this function.

Reserved

CSZ4

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

000

Table 22.

DDX® power output mode

Bit

R/W

RST

Name

Description

1:0

OM[1:0]

DDX® power output mode:

Selects configuration of DDX® output.

Table 23.

DDX® output modes

OM[1,0]

Output stage - mode

Not used

Recommended

Variable compensation

Table 24.

DDX® compensating pulse

CSZ[4:0]

Compensating pulse size

00000

0 clock period compensating pulse size

00001

1 clock period compensating pulse size

……

10000

16 clock period compensating pulse size

……

11111

31 clock period compensating pulse size

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