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STA328

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6.6

Configuration register F (addr 0x05)

Setting the IDE bit enables this function, which looks at the input I2S data and clocking and

will automatically mute all outputs if the signals are perceived as invalid.

Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible

artifacts when input clocking is lost.

EAPD

PWDN

ECLE

Reserved

BCLE

IDE

OCFG1

OCFG0

Table 40.

Output configuration selection

Bit

R/W

RST

Name

Description

1:0

OCFG[1:0]

Output configuration selection

00: 2-channel (full-bridge) power, 1-channel

DDX® is

default

Table 41.

Output configuration selection

OCFG[1:0]

Output power configuration

2 channel (full-bridge) power, 1 channel

DDX®:

1A/1B

◊ 1A/1B

2A/2B

◊ 2A/2B

2 (half-bridge) and 1 (full-bridge) on-board power:

◊ 1A binary

◊ 1B binary

3A/3B

◊ 2A/2B binary

Reserved

1 channel mono-parallel:

◊ 1A/1B

◊ 2A/2B

Table 42.

Invalid input detect mute enable

Bit

R/W

RST

Name

Description

2RW

IDE

Invalid input detect auto-mute enable:

0: disabled

1: enabled

Table 43.

Binary clock loss detection enable

Bit

R/W

RST

Name

Description

3RW

BCLE

Binary output mode clock loss detection enable

0: disabled

1: enabled

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