MPC8313E datasheet(53/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

SPI

Figure 38 provides the AC test load for the SPI.

Figure 38. SPI AC Test Load

Figure 39 through Figure 40 represent the AC timing from Table 59. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 39 shows the SPI timing in Slave mode (external clock).

Figure 39. SPI AC Timing in Slave Mode (External Clock) Diagram

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of SYS_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI

outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are

valid (V).

Table 59. SPI AC Timing Specifications 1

Characteristic

Symbol 2

Min

Max

Unit

Output

Z0 = 50 Ω

NVDD/2

RL = 50 Ω

SPICLK (input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

MPC8313E Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc