CA3140, CA3140A

FN957 Rev.10.01

Page 21 of 21

Feb 19, 2026

Metallization Mask Layout

Package Outline Drawings

The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package

information is the most current data available and is subject to change without revision of this document.

Revision History

Dimensions in parenthesis are in millimeters and are derived

from the basic inch dimensions as indicated. Grid graduations

are in mils (10-3 inch).

The photographs and dimensions represent a chip when it is

part of the wafer. When the wafer is cut into chips, the cleavage

angles are 57o instead of 90 with respect to the face of the

chip. Therefore, the isolated chip is actually 7 mils (0.17mm)

larger in both dimensions.

62-70

(1.575-1.778)

4-10

(0.102-0.254)

60

50

40

30

20

10

0

58-66

(1.473-1.676)

50

40

30

20

10

61

0

60 65

Revision

Date

Description

10.01

Feb 19, 2026

▪ Updated Ordering Information table.

▪ Added Revision History section.

▪ Updated POD M8.15 to the latest version; changes are as follows.

• Placed into latest template.

• Added coplanarity spec