LAN9312 datasheet(295/458 Pages) SMSC

295 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

295

Revision 1.2 (04-08-08)

DATASHEET

Note 14.53

The Pause and Asymmetric Pause bits are loaded into the PHY registers by the EEPROM

Loader.

Note 14.54

The default value of this bit is determined by the Manual Flow Control Enable Strap

(manual_FC_strap_x). When the Manual Flow Control Enable Strap is 0, this bit defaults

to 1 (symmetric pause advertised). When the Manual Flow Control Enable Strap is 1, this

bit defaults to 0 (symmetric pause not advertised). Configuration strap values are latched

upon the de-assertion of a chip-level reset as described in Section 4.2.4, "Configuration

Straps," on page 40. Refer to Section 4.2.4, "Configuration Straps," on page 40 for

configuration strap definitions.

Note 14.55

The default value of this bit is determined by the logical OR of the Auto-Negotiation strap

(autoneg_strap_x) with the logical AND of the negated speed select strap (speed_strap_x)

and (duplex_strap_x). Table 14.8 defines the default behavior of this bit. Configuration

strap values are latched upon the de-assertion of a chip-level reset as described in Section

4.2.4, "Configuration Straps," on page 40. Refer to Section 4.2.4, "Configuration Straps,"

on page 40 for configuration strap definitions.

Note 14.56

The default value of this bit is determined by the logical OR of the Auto-Negotiation strap

(autoneg_strap_x) and the negated speed strap (speed_strap_x). Table 14.9 defines the

default behavior of this bit. Configuration strap values are latched upon the de-assertion

of a chip-level reset as described in Section 4.2.4, "Configuration Straps," on page 40.

Refer to Section 4.2.4, "Configuration Straps," on page 40 for configuration strap

definitions.

10BASE-T Full Duplex

This bit determines the advertised 10BASE-T full duplex capability.

0: 10BASE-T full duplex ability not advertised

1: 10BASE-T full duplex ability advertised

R/W

Note 14.55

Table 14.8

10BASE-T Half Duplex

This bit determines the advertised 10BASE-T half duplex capability.

0: 10BASE-T half duplex ability not advertised

1: 10BASE-T half duplex ability advertised

R/W

Note 14.56

Table 14.9

4:0

Selector Field

This field identifies the type of message being sent by Auto-Negotiation.

00001: IEEE 802.3

R/W

00001b

Table 14.8 10BASE-T Full Duplex Advertisement Default Value

autoneg_strap_x

speed_strap_x

duplex_strap_x

Default 10BASE-T Full Duplex (Bit 6) Value

BITS

DESCRIPTION

TYPE

DEFAULT

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