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LAN9312 Datasheet(PDF) 438 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 438 Page - SMSC Corporation |
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438 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.2 (04-08-08) 438 SMSC LAN9312 DATASHEET 14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR) This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Buffer Manager Interrupt Pending Register (BM_IPR). All Buffer Manager interrupts are masked by setting the Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to Chapter 5, "System Interrupts," on page 49 for more information. Register #: 1C20h Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31:1 RESERVED RO - 0 Interrupt Mask When set, this bit masks interrupts from the Buffer Manager. The status bits in the Buffer Manager Interrupt Pending Register (BM_IPR) are not affected. R/W 1b |
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