AS7343L datasheet(29/53 Pages) AMSOSRAM

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AS7343L

Datasheet

• PUBLIC

DS001038

• v2-00 • 2022-Aug-12

│ 28

ASTEP Register (Address 0xD4, 0xD5)

Figure 27:

ASTEP Register

Addr: 0xD4, 0xD5

ASTEP

Bit

Bit Name

Default

Access

Bit Description

7:0

ASTEP 0xCA

999

Integration Time Step Size.

Sets the integration time per step in increments of

2.78 µs. The default value is 999.

VALUE

STEP SIZE

2.78 µs

2.78 µs x (n+1)

15:8

ASTEP 0xCB

599

1.67 ms

999

2.78 ms

17999

50 ms

65534

182 ms

65535

Reserved, do not use

WTIME Register (Address 0x83)

If wait is enabled (WEN = “1” register 0x80), each new measurement is started based on WTIME. It is

necessary for WTIME to be sufficiently long for spectral integration and any other functions to be

completed within the period. The device will warn the user if the timing is configured incorrectly. If

WTIME is too short, then SP

_TRIG in register STATUS6 (ADDR: 0xA7) will be set to “1”.

Figure 28:

WTIME Register

Addr: 0x83

WTIME

Bit

Bit Name

Default

Access

Bit Description

7:0

WTIME

0x00

Spectral Measurement Wait Time.

8-bit value to specify the delay between two

consecutive spectral measurements.

Value

Wait Cycles

Wait Time

0x00

2.78 ms

0x01

5.56 ms

2.78 ms x (n+1)

0xff

256

711 ms

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