9.2 Layout

9.2.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier like the OPA955 requires careful attention to

board layout parasitics and external component types. Recommendations that optimize performance include:

• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the

output and inverting input pins can cause instability. To reduce unwanted capacitance, cut out the power and

ground traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken

elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is less

than 0.15pF, consider using two series resistors, each of half the value of a single resistor in the feedback

loop to minimize the parasitic capacitance from the resistor.

• Minimize the distance (less than 0.25-in) from the power-supply pins to high-frequency bypass

capacitors. Use high-quality, 100pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings

at least three times greater than the amplifiers maximum power supplies. This configuration makes sure

that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth

specification. At the device pins, do not allow the ground and power plane layout to be in close proximity

to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and

the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.

Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be used on the

supply pins. Place these decoupling capacitors further from the device. Share the decoupling capacitors

among several devices in the same area of the printed circuit board (PCB).

• Careful selection and placement of external components preserves the high-frequency performance

of the OPA955. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall

layout. Never use wire-wound resistors in a high-frequency application. Because the output pin and inverting

input pin are the most sensitive to parasitic capacitance, always position the feedback and series output

resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting

input termination resistors) close to the package. Even with a low parasitic capacitance shunting the

external resistors, high resistor values create significant time constants that can degrade performance. When

configuring the OPA955 as a voltage amplifier, keep resistor values as low as possible and consistent

with load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and

minimizes the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power

consumption because RF and RG become part of the output load network of the amplifier.

9.2.2 Layout Example

Place gain and feedback resistors

close to pins to minimize stray

capacitance

Place bypass capacitor

close to power pins

Connect the thermal pad to the

negative supply pin

1

8

2

7

3

6

4

5

CBYP

RF

RG

RS

CBYP

Thermal

Pad

Connect PD to VS+ to enable the

amplifier

NC (Pin 2) isolates the IN- and FB

pins thereby reducing capacitive

coupling

Ground and power plane removed

from inner layers. Ground fill on

outer layers also removed

Ground and power plane exist on

inner layers.

CBYP

RF

RG

+

±

VS-

CBYP

VS+

Representative schematic

RS

Figure 9-2. Layout Recommendation

OPA955

SLOSEE6 – JULY 2026

www.ti.com

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