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TAS2020RBGR Datasheet(PDF) 36 Page - Texas Instruments |
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TAS2020RBGR Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 79 page  7.1.1 Page Register (Address = 0h) [Reset = 00h] Return to the Summary Table. The device's memory map is divided into pages and books. This register sets the page. Table 7-2. Page Register Field Descriptions Bit Field Type Reset Description 7-0 PAGE[7:0] R/W 0h Sets the device page. 0h = Page 0 1h = Page 1 FFh = Page 255 7.1.2 SW_RESET Register (Address = 1h) [Reset = 00h] Return to the Summary Table. Asserting Software Reset will place all register values in their default POR (Power on Reset) state. Table 7-3. SW_RESET Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved 0 SW_RESET R/W 0h Software reset. Bit is self clearing. 0h = Don't reset 1h = Reset 7.1.3 PWR_CTL Register (Address = 2h) [Reset = 03h] Return to the Summary Table. Sets device's mode of operation and Power Configuration. Table 7-4. PWR_CTL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h Reserved 1-0 MODE[1:0] R/W 3h Device operational mode. 0h = Active 1h = Reserved 2h = Software Shutdown 3h = Wake-up and Shutdown on ASI Clock 7.1.4 DEVICE_CFG_01 Register (Address = 3h) [Reset = 81h] Return to the Summary Table. This register configures various device modes. Table 7-5. DEVICE_CFG_01 Register Field Descriptions Bit Field Type Reset Description 7-6 EFFICIENCY_MODE[1:0] R/W 2h Device operational mode. 0h = Music Efficiency and Noise Gate mode disabled 1h = Noise Gate Mode Only 2h = Music Efficiency Only 3h = Music Efficiency and Noise Gate mode 5-2 RESERVED R 0h Reserved TAS2020 SLASFD4A – AUGUST 2024 – REVISED JULY 2026 www.ti.com 36 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TAS2020 |
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