RX72N datasheet(120/179 Pages) RENESAS

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R01DS0343EJ0120 Rev.1.20

Page 120 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.6

POE

Note 1. tPBcyc: PCLKB cycle

Figure 2.42

POE# Input Timing

Figure 2.43

Output Disable Time for POE in Response to Transition of the POEn# Signal Level

Table 2.33

POE Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min. Typ.

Max.

Unit*1

Test Conditions

POE

POEn# input pulse width

(n = 0, 4, 8, 10, 11)

tPOEW

1.5

—

tPBcyc Figure 2.42

Output

disable time

Transition of the POEn#

signal level

tPOEDI

—

5 PCLKB + 0.24

µs

Figure 2.43

When detecting falling edges

(ICSRm.POEnM[3:0] = 0000

(m = 1 to 5; n = 0, 4, 8, 10, 11))

Simultaneous conduction

of output pins

tPOEDO

—

3 PCLKB + 0.2

µs

Figure 2.44

tPOEDS

—

1 PCLKB + 0.2

µs

Figure 2.45

Time for access to the register

is not included.

Oscillation stop detection

tPOEDOS

—

µs

Figure 2.46

POEn# input

(n = 0, 4, 8, 10, 11)

PCLKB

tPOEW

POEn# input

(n = 0, 4, 8, 10, 11)

MTU PWM output pins

Outputs disabled

tPOEW

tPOEDI

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