RX72N datasheet(122/179 Pages) RENESAS

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R01DS0343EJ0120 Rev.1.20

Page 122 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.7

POEG

Note 1. tPBcyc: PCLKB cycle

Figure 2.47

POEG Input Timing

Figure 2.48

Output Disable Time for POEG via Detection Flag in Response to the Input Level Detection of the

GTETRGn pin

Table 2.34

POEG Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min. Typ.

Max.

Unit*1

Test Conditions

POEG GTETRGn input pulse width (n = A to D)

tPOEGW

1.5

—

tPBcyc Figure 2.47

Output

disable time

Input level detection of the

GTETRGn pin (via flag)

tPOEGDI

—

3 PCLKB + 0.34

µs

Figure 2.48

When the digital noise filter is

not in use (POEGGn.NFEN = 0

(n = A to D))

Detection of the output

stopping signal from

GPTW (deadtime error,

simultaneous high output,

or simultaneous low

output)

tPOEGDE

—

0.5

µs

Figure 2.49

tPOEGDS

—

1 PCLKB + 0.3

µs

Figure 2.50

Time for access to the register

is not included.

Oscillation stop detection

tPOEGDOS

—

µs

Figure 2.51

GTETRGn input

(n = A to D)

PCLKB

tPOEGW

GTETRGn input

(n = A to D)

GPTW PWM output pins

Outputs disabled

tPOEGDI

tPOEGW

POEGGn.PIDF flag

(n = A to D)

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