RX72N datasheet(150/179 Pages) RENESAS

150 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 150 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.18

PDC

Note 1. tPBcyc: PCLKB cycle

Figure 2.91

PDC Input Clock Timing

Figure 2.92

PDC Output Clock Timing

Table 2.47

PDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.*1

Max.

Unit

Test

Conditions

PDC

PIXCLK input cycle time

tPIXcyc

—

Figure 2.91

PIXCLK input high pulse width

tPIXH

—

PIXCLK input low pulse width

tPIXL

—

PIXCLK rising time

tPIXr

—5

PIXCLK falling time

tPIXf

—5

PCKO output cycle time

tPCKcyc

2 × tPBcyc

—

Figure 2.92

PCKO output high pulse width

tPCKH

(tPCKcyc – tPCKr – tPCKf)/2 – 3

—

PCKO output low pulse width

tPCKL

(tPCKcyc – tPCKr – tPCKf)/2 – 3

—

PCKO rising time

tPCKr

—5

PCKO falling time

tPCKf

—5

VSYNC/HSYNC input setup time

tSYNCS

—

Figure 2.93

VSYNC/HSYNC input hold time

tSYNCH

5—

PIXD input setup time

tPIXDS

—

PIXD input hold time

tPIXDH

5—

tPIXcyc

tPIXH

tPIXf

tPIXL

tPIXr

PIXCLK input

tPCKcyc

tPCKH

tPCKf

tPCKL

tPCKr

PCKO pin output

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