RX72N datasheet(152/179 Pages) RENESAS

152 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 152 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.19

GLCDC

Note 1. Parallel RGB888,666,565: Max. 27 MHz

Serial RGB888: Max. 30 MHz (4x speed)

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc) to indicate group membership appended to their names as groups.

For the GLCDC interface, the AC portion of the electrical characteristics is measured for each group.

If we use group “-A” and “-B” combination, “LCD data output Delay timing (tDD)” is Min = –5.0 ns, Max = 5.5 ns.

Figure 2.94

LCD_EXTCLK Clock Input Timing

Figure 2.95

LCD_CLK Clock Output Timing

Table 2.48

GLCDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

LCD_EXTCLK Input clock frequency

tEcyc

—

30*1

MHz

Figure 2.94

LCD_EXTCLK Input clock Low pulse width

tWL

0.45

—

0.55

tEcyc

LCD_EXTCLK Input clock High pulse width

tWH

0.45

—

0.55

tEcyc

LCD_CLK Output clock frequency

tLcyc

—

30*1

MHz

Figure 2.95

LCD_CLK Output clock Low pulse width

tLOL

0.4

—

0.6

tLcyc

LCD_CLK Output clock High pulse width

tLOH

0.4

—

0.6

tLcyc

LCD_CLK Output clock rise time

tLOR

——

LCD_CLK Output clock fall time

tLOF

——

LCD data output Delay timing

tDD

–3.5*2

—4*2

Figure 2.96

1/2 Vcc

VIH VIH

VIL

tDcyc, tEcyc

tWH

tWL

LCD_EXTCLK

tLcyc

tLOL

tLOH

tLOF

tLOR

LCD_CLK

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