RX72N datasheet(161/179 Pages) RENESAS

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R01DS0343EJ0120 Rev.1.20

Page 161 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.9

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Note:

The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,

and Vdet2 for the POR/ LVD.

Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.

Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.

Figure 2.102

Power-on Reset Timing

Table 2.58

Power-on Reset Circuit and Voltage Detection Circuit Characteristics

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

Voltage detection

level

Power-on

reset (POR)

Low power consumption

function disabled*1

VPOR

2.5

2.6

2.7

Figure 2.102

Low power consumption

function enabled*2

1.8

2.25

2.7

Voltage detection circuit (LVD0)

Vdet0_1

2.84

2.94

3.04

Figure 2.103

Vdet0_2

2.77

2.87

2.97

Vdet0_3

2.70

2.80

2.90

Voltage detection circuit (LVD1)

Vdet1_1

2.89

2.99

3.09

Figure 2.104

Vdet1_2

2.82

2.92

3.02

Vdet1_3

2.75

2.85

2.95

Voltage detection circuit (LVD2)

Vdet2_1

2.89

2.99

3.09

Figure 2.105

Vdet2_2

2.82

2.92

3.02

Vdet2_3

2.75

2.85

2.95

Internal reset time

Power-on reset time

tPOR

—

4.6

—

Figure 2.102

LVD0 reset time

tLVD0

—

0.70

—

Figure 2.103

LVD1 reset time

tLVD1

—

0.57

—

Figure 2.104

LVD2 reset time

tLVD2

—

0.57

—

Figure 2.105

Minimum VCC down time

tVOFF

200

—

µs

Figure 2.102,

Figure 2.103

Response delay time

tdet

—

200

µs

Figure 2.102 to

Figure 2.105

LVD operation stabilization time (after LVD is enabled)

td(E-A)

—

µs

Figure 2.104,

Figure 2.105

Hysteresis width (LVD1 and LVD2)

V LVH

—70

—

Internal reset signal

(Low is valid)

VCC

tVOFF

tdet tPOR

tdet

tPOR

tdet

VPOR

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