RX140 datasheet(60/121 Pages) RENESAS

60 / 121 page

R01DS0379EJ0120 Rev.1.20

Page 60 of 121

Nov 22, 2024

RX140 Group

2. Electrical Characteristics

2.5.3

Timing of Recovery from Low Power Consumption Modes

Note 1. When multiple oscillators are operating before entry to software standby mode, the oscillation stabilization wait time will be

selected as the largest value among those for the operating oscillators.

Note 2. For n, the largest value is selected from among the internal clock division settings.

Note 3. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization

wait time and the time required for operations by the sequencer before release from software standby mode.

Table 2.40

Timing of Recovery from Low Power Consumption Modes (1)

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

Oscillation

stabilization

wait time*1

High-speed

operating

mode/

Middle-

speed

operating

mode

Main clock

oscillator

operating

Main clock oscillator

operating

tSBYOSCWTMC

——

tLOCO + (16 +

Number of

cycles specified

MOSCWTCR) /

fLOCO + 2 /

fMOSC + 1 /

fICLK

µs

Main clock oscillator

and PLL circuit

operating

tSBYOSCWTPC

——

tLOCO + (288 +

Number of

cycles specified

MOSCWTCR) /

fLOCO + 2 / fPLL

+ 1 / fICLK

Sub-clock oscillator operating

tSBYOSCWTSC

——

3 / fSOSC + 1 /

fICLK

High-speed on-chip oscillator

operating

tSBYOSCWTHO

——

tLOCO + 16 /

fLOCO + 2 /

fHOCO + 1 /

fICLK

Low-speed on-chip oscillator

operating

tSBYOSCWTLO

——

tLOCO

+ 1 / fICLK

Time required for operations by the sequencer before release

from software standby mode*2

tSBYSEQ

——

4 / fLOCO + 11 /

fICLK + 3 /

fPCLKB + 3n /

fsource clock

Recovery

time from

software

standby

mode*3

High-speed

operating

mode/

Middle-

speed

operating

mode

Main clock

oscillator

operating

Main clock oscillator

operating

tSBYMC

——

tSBYOSCWTMC +

tSBYSEQ

Figure 2.24

Main clock oscillator

and PLL circuit

operating

tSBYPC

——

tSBYOSCWTPC +

tSBYSEQ

Sub-clock oscillator operating

tSBYSC

——

tSBYOSCWTSC +

tSBYSEQ

High-speed on-chip oscillator

operating

tSBYHO

——

tSBYOSCWTHO +

tSBYSEQ

Low-speed on-chip oscillator

operating

tSBYLO

——

tSBYOSCWTLO +

tSBYSEQ

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