R5F52607ADFN datasheet(82/142 Pages) RENESAS

82 / 142 page

R01DS0430EJ0100 Rev.1.00

Page 82 of 142

Jul 31, 2024

RX260 Group, RX261 Group

2. Electrical Characteristics

Note 1. tPBcyc: PCLKB cycle

Note 2. When SEMR.ABCS = 1 and SEMR.BGDM = 1

Figure 2.37

SCK Clock Input Timing

SCI

(channel 12)

Input clock cycle time

Asynchronous

tScyc

4—

tPBcyc Figure 2.37

Clock synchronous 2.4 V ≤ VCC ≤ 5.5 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—20

Input clock fall time

tSCKf

—20

Output clock cycle time

Asynchronous*2

tScyc

8—

tPBcyc Figure 2.38

Clock synchronous 2.4 V ≤ VCC ≤ 5.5 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

1.8 V ≤ VCC ≤ 5.5 V

tSCKr

—20

1.6 V ≤ VCC < 1.8 V

—

Output clock fall time

1.8 V ≤ VCC ≤ 5.5 V

tSCKf

—20

1.6 V ≤ VCC < 1.8 V

—

Transmit data delay time

(master)

Clock synchronous 1.8 V ≤ VCC ≤ 5.5 V

tTXD

—40

1.6 V ≤ VCC < 1.8 V

—

Transmit data delay time

(slave)

Clock synchronous 2.4 V ≤ VCC ≤ 5.5 V

—

1.8 V ≤ VCC < 2.4 V

—

100

1.6 V ≤ VCC < 1.8 V

—

125

Receive data setup time

(master)

Clock synchronous 2.7 V ≤ VCC ≤ 5.5 V

tRXS

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

1.6 V ≤ VCC < 1.8 V

110

—

Receive data setup time

(slave)

Clock synchronous 1.8 V ≤ VCC ≤ 5.5 V

—

1.6 V ≤ VCC < 1.8 V

—

Receive data hold time

Clock synchronous

tRXH

—

Table 2.51

SCI Timing (2/2)

Conditions: 1.6 V ≤ VCC ≤ 5.5 V, 1.6 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF

Item

Symbol

Min.

Max.

Unit

Test

Conditions

tSCKW

tSCKr

tSCKf

tScyc

SCKn

n = 1, 5, 6, 12

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