R5F52607ADFN datasheet(2/142 Pages) RENESAS

2 / 142 page

R01DS0430EJ0100 Rev.1.00

Page 2 of 142

Jul 31, 2024

RX260 Group, RX261 Group

1. Overview

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of the products in

different packages.

Table 1.1 shows the outline of maximum specifications. The peripheral functions and the number of their channels vary

depending on the number of pins of the package. For details, see Table 1.2, Comparison of Functions for Different

Packages.

Table 1.1

Outline of Specifications (1/6)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 64 MHz

 32-bit RX CPU (RX v3)

 Minimum instruction execution time: One instruction per clock cycle

 Address space: 4-Gbyte linear

 Register set

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 111 instructions

Standard provided instructions: 111

Basic instructions: 77

Single precision floating point instructions: 11

DSP instructions: 23

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

 On-chip divider: 32-bit ÷ 32-bit → 32 bits

 Barrel shifter: 32 bits

 Memory protection unit (MPU)

FPU

 Single precision (32-bit) floating-point number

 Data types and exceptions in conformance with the IEEE754 standard

Memory

ROM

 Capacity: 512 Kbytes, 384 Kbytes, 256 Kbytes

 32 MHz ≤: No-wait cycle access

 32 MHz to 64 MHz: One-wait cycle access

 Programming/erasing method:

Serial programming (asynchronous serial communication/USB communication), self-

programming

RAM

 Capacity: 128 Kbytes

 64 MHz, no-wait memory access

 Parity error detection

E2 DataFlash

 Capacity: 8 Kbytes

 Number of erase/write cycles: 1,000,000 (typ.)

MCU operating mode

Single-chip mode

Clock

Clock generation circuit

 Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-

chip oscillator, PLL frequency synthesizer, PLL2 frequency synthesizer, and IWDT-

dedicated on-chip oscillator

 Oscillation stop detection: Available

 Clock frequency accuracy measurement circuit (CAC)

 Independent settings for the system clock (ICLK), peripheral module clock (PCLKA,

PCLKB, and PCLKD), and FlashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with

the system clock (ICLK): 64 MHz (at max.)

Peripheral modules of GPTW, and the ECC function control registers in the CANFD

module run in synchronization with PCLKA: 64 MHz (at max.)

ADCLK in the S12AD runs in synchronization with PCLKD: 64 MHz (at max.)

Other peripheral modules run in synchronization with PCLKB: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 64 MHz (at max.)

R5F52607ADFN Datasheet(PDF) 2 Page - Renesas Technology Corp

R5F52607ADFN Datasheet(HTML) 2 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL