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SSD1309Z Datasheet(PDF) 21 Page - Solomon Systech Limited |
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SSD1309Z Datasheet(HTML) 21 Page - Solomon Systech Limited |
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21 / 57 page ![]() Solomon Systech Jul 2011 P 26/62 Rev 1.1 SSD1309 8.8 Power ON and OFF sequence The following figures illustrate the recommended power ON and power OFF sequence of SSD1309 Power ON sequence: 1. Power ON VDD 2. After VDD become stable, set RES# pin LOW (logic low) for at least 3us (t1) (3) and then HIGH (logic high). 3. After set RES# pin LOW (logic low), wait for at least 3us (t2). Then Power ON VCC. (1) 4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after 100ms (tAF). Figure 8-16 : The Power ON sequence Power OFF sequence: 1. Send command AEh for display OFF. 2. Power OFF VCC. (1), (2) 3. Power OFF VDD after tOFF. (4) (where Minimum t OFF=0ms, typical tOFF=100ms) Figure 8-17 : The Power OFF sequence OFF VDD VDD VCC Send command AEh for display OFF OFF VCC OFF OFF tOFF Note: (1) V CC should be kept float (i.e. disable) when it is OFF. (2) Power Pins (V DD, VCC) can never be pulled to ground under any circumstance. (3) The register values are reset after t 1. (4) V DD should not be Power OFF before VCC Power OFF. OFF ON VDD RES# ON VCC Send AFh command for Display VDD RES# OFF t1 SEG/COM tAF ON OFF VCC GND t2 |
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