9SQ445 datasheet(13/31 Pages) RENESAS

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R31DS0066EU0104 August 5, 2026

9SQ445 Datasheet

1 Guaranteed by design and characterization, not 100% tested in production.

2 Control input must be monotonic from 20% to 80% of input swing.

3 Refers to device differential output clock.

Figure 2. Side Band Interface Timing Diagram

Table 14. Side Band Interface

Parameter

Symbol

Conditions

Minimum Typical Maximum

Units

Notes

Clock Period

tPERIOD Clock period.

—

Setup Time to Clock

tSETUP

SHFT setup to CLK rising edge.

—

Data set up time

tDSU

DATA setup to CLK rising edge.

—

Data hold time

tDHOLD DATA hold after CLK rising edge.

—

Delay time

tDELAY

Delay from CLK rising edge to LD# falling edge.

—

Propagation Delay

tPD

Delay from LD# falling edge to next output

configuration taking effect.

—

clocks

Slew Rate

tSLEW

CLK input (between 20% and 80%).

0.7

0.9

1.5

V/ns

Output Impedance

ZOUT

SBI_OUT output impedance.

—

1st bit

Current O/P Config.

Next O/P

Config.

tSETUP

tPERIOD

tDSU

tDHOLD

tSHOLD

tEN/

DIS

SBI_IN

SBI_CLK

SHFT_LD#

OUTPUT

1st bit out

(1st bit in from last shift)

tCO

SBI_OUT

2nd bit out

(2nd bit in from last shift)

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