DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
17
Version: DM9010-DS-P03
Apr. 28, 2005
TXPLH
TX Packet Length High Byte Register
FDH
XXH
ISR
Interrupt Status Register
FEH
00H
IMR
Interrupt Mask Register
FFH
00H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
P = power on reset default value
H = hardware reset default value
S = software reset default value
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
EXT_PHY
PH0,RW
Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
6
WAKEEN
P0,RW
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
5
RESERVED
0,RO
Reserved
4
FCOL
PHS0,RW Force Collision Mode, used for testing
3
FDX
PHS0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
2:1
LBK
PHS00,
RW
Loopback Mode
Bit
2 1
0
0
Normal
0
1
MAC Internal Loopback
1
0
Internal PHY 100M mode digital Loopback
1
1
(Reserved)
0
RST
PH0,RW
Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
Name
Default
Description
7
SPEED
X,RO
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
6
LINKST
X,RO
Link Status 0:link failed 1:link OK, when Internal PHY is used
5
WAKEST
P0,
RW/C1
Wakeup Event Status. Clears by read or write 1
This bit will not be affected after software reset
4
RESERVED
0,RO
Reserved
3
TX2END
PHS0,
RW/C1
TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2
2
TX1END
PHS0,
RW/C1
TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
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