DATASHEET

DECEMBER 13, 2023

1

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Low Skew 1 to 4 Clock Buffer

524S

Description

The 524S is a low skew, single input to four output, clock

buffer. The 524S has best in class additive phase jitter of sub

50 fsec. The 524S is Power Down Tolerant (PDT). PDT

designated inputs may be driven before VDD is applied,

without damage to the device.

Renesas makes many non-PLL and PLL based low skew

output devices as well as Zero Delay Buffers to synchronize

clocks. Contact us for all of your clocking needs.

Features

• Low additive phase jitter RMS: 50fs

• Extremely low skew outputs (50ps)

• Low cost clock buffer

• Packaged in 8-SOIC and 8-DFN, Pb-free

• ICLK is PDT and may be driven before VDD is applied

• Direct-coupled signal path suitable for 1pps clocks

• Input/Output clock frequency up to 200MHz

• Non-inverting output clock

• Ideal for networking clocks

• Operating Voltages: 1.8V to 3.3V

• Advanced, low power CMOS process

• Extended temperature range (-40°C to +105°C)

Block Diagram

Q0

ICLK

Q1

Q2

Q3