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ML22Q533 Datasheet(PDF) 15 Page - Rohm |
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ML22Q533 Datasheet(HTML) 15 Page - Rohm |
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15 / 178 page  FEDL22Q53X-02 ML22Q53X ● AC Characteristics (Clock Synchronous Serial Interface) SPVDD=SPOVDD ≥DV DD=IOVDD=2.7 to 5.5V, DGND=SPGND=SPOGND=0V, Ta=-40 to +105°C, Load capacitance of output pin =15pF(Max.) Parameter Symbol Condition Min. Typ. Max. Unit CSB input enable time from IRON falling edge tEIRON — 1000 — — ns CSB hold time from IRON rising edge tIRONH — 1000 — — ns SCK setup time from CSB falling edge tSCKS — 100 — — ns SCK input enable time from CSB falling edge tESCK — 100 — — ns SCK hold time from CSB rising edge tCSH — 100 — — ns Data floating time from CSB rising edge tDOZ RL=3KΩ — — 100 ns Data setup time from SCK tDIS — 50 — — ns Data hold time from SCK tDIH — 50 — — ns Data output delay time from SCK tDOD — — — 90 ns SCK "H" level pulse width tSCKH — 100 — — ns SCK "L" level pulse width tSCKL — 100 — — ns CBUSYB output delay time from SCK tDBSY — — — 90 ns <When rewriting the flash memory using the clock synchronous serial interface> SPVDD=SPOVDD ≥DV DD=IOVDD=2.7 to 5.5V, DGND=SPGND=SPOGND=0V, Ta=-40 to +105°C, Load capacitance of output pin =15pF(Max.) Parameter Symbol Condition Min. Typ. Max. Unit CSB input enable time from IRON falling edge tEIRON — 1000 — — ns CSB hold time from IRON rising edge tIRONH — 1000 — — ns SCK setup time from CSB falling edge tSCKS — 125 — — ns SCK input enable time from CSB falling edge tESCK — 125 — — ns SCK hold time from CSB rising edge tCSH — 125 — — ns Data floating time from CSB rising edge tDOZ RL=3KΩ — — 125 ns Data setup time from SCK tDIS — 50 — — ns Data hold time from SCK tDIH — 50 — — ns Data output delay time from SCK tDOD — — — 110 ns SCK "H" level pulse width tSCKH — 125 — — ns SCK "L" level pulse width tSCKL — 125 — — ns 15/178 |
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