CN-0335

Circuit Note

Rev. A | Page 4 of 8

Effect of Resistor Temperature Coefficients on Overall

Error

Equation 1 shows that the output voltage is a function of five

resistors: R1, R2, R4, R5, and R6. The sensitivity of the full-scale

output voltage at TP1 to small changes in each of the five

resistors was calculated using a simulation program. The input

voltage to the circuit was +10 V. The individual sensitivities

calculated were SR1 = 0.19, SR2 = 0.19, SR4 = 0.39, SR5 = 0.11, SR6 =

0.50. Assuming the individual temperature coefficients combine

in a root-sum-square (rss) manner, then the overall full-scale

drift using 100 ppm/°C resistors is approximately:

Full scale drift =

=100 ppm/°C √(SR12 + SR22 + SR42 + SR52 + SR62)

=100 ppm/°C √(0.192 + 0.192 + 0.392 + 0.112 + 0.502)

= 69 ppm/°C

The full scale drift of 69 ppm/°C corresponds to 0.0069%

FSR/°C. Using 25 ppm/°C resistors reduces the drift error to

0.25 × 69 ppm/°C = 17 ppm/°C, or 0.0017% FSR/°C.

Effect of Active Component Temperature Coefficients on

Overall Error

The dc offsets of the AD8606 op amps and the AD7091R ADC

are eliminated by the calibration procedure.

The offset drift of the ADC AD7091R internal reference is

4.5 ppm/°C typical and 25 ppm/°C maximum.

The offset drift of the AD8606 op amp is 1μV/°C typical and

4.5μV/°C maximum.

The error due to the U1A input AD8606 is referenced to the

2.3 V output range and is therefore 2 ppm/°C. The error due to

the U1B reference buffer is referenced to 2.5 V and is also

approximately 2 ppm/°C.

The total drift error is summarized in Table 1. These errors do

not include the ±1 LSB integral nonlinearity error of the AD7091R.

Note that resistor drift is the largest contributor to total drift if

50 ppm/°C or 100 ppm/°C resistors are used, and the drift due

to active components can be neglected.

Table 1. Error Due to Temperature Drift

Error Source

Total Error

Resistors (1%, 100 ppm/°C)

±0.0069% FSR/°C

AD7091R (∆VVREF/∆T = 25 ppm/°C)

±0.0025% FSR/°C

AD8606, U1A (∆VOS/∆T= 4.5 μV/°C), 2

ppm/°C, Referenced to 2.3 V

±0.0002% FSR/°C

AD8606, U1B (∆VOS/∆T= 4.5 μV/°C), 2

ppm/°C, Referenced to 2.5 V

±0.0002% FSR/°C

Total FSR Error Temperature Coefficient

(100 ppm/°C Resistors)

±0.0098% FSR/°C

Total % FSR Error for ∆T=±10°C (100 ppm/°C

Resistors)

±0.098% FSR

Total % FSR Error for ∆T=±10°C (25 ppm/°C

Resistors)

±0.046% FSR

Test Data Before and After Two-Point Calibration

To perform the two-point calibration, −10 V is first applied to

the input, and the ADC output code is recorded as Code_1.

Then +10 V is applied to the input, and the ADC output code is

recorded as Code_2. The gain factor is calculated by

Code_1

Code_2 −

=

V

20

GF

The input voltage can now be calculated corresponding to any

output code, Code_x, using the equation:

)

(

V

10

Code_1

Code_x −

+

−

=

GF

V

IN

.

The error before calibration is obtained by comparing the ideal

transfer function calculated using the nominal values of the

components, and real circuit transfer function without

calibration. The tested circuits have been built with resistors

having ±1% tolerance. The test results do not include

temperature changes.

The graph in Figure 3 shows test results for percent error (FSR)

before and after calibration at ambient temperature. As it is shown,

the maximum error before calibration is about 0.23% FSR.

After calibration, the error decreases to ±0.03% FSR, which

approximately corresponds to 1 LSB error of the ADC.

0.25

0.20

0.15

0.10

0.05

0

–0.05

–10

–5

0

5

10

INPUT VOLTAGE (V)

ERROR BEFORE CALIBRATION

ERROR AFTER CALIBRATION

Figure 3. Circuit Test Error Before and After Room Temperature Calibration

PCB Layout Considerations

In any circuit where accuracy is crucial, it is important to consider

the power supply and ground return layout on the board. The

PCB should isolate the digital and analog sections as much as

possible. The PCB for this system was constructed in a simple

2-layer stack up, but a 4-layer stack up gives better EMS. See the

MT-031 Tutorial for more information on layout and grounding

and the MT-101 Tutorial for information on decoupling

techniques. Decouple the power supply to AD8606 with 10 μF

and 0.1 μF capacitors to properly suppress noise and reduce ripple.

Place the capacitors as close to the device as possible with the

0.1 μF capacitor having a low ESR value. Ceramic capacitors are

advised for all high frequency decoupling. Power supply lines

should have as large trace width as possible to provide a low

impedance path and to reduce glitch effects on the supply line.