CN-0335

Circuit Note

Rev. A | Page 2 of 8

CIRCUIT DESCRIPTION

The circuit consists of an input signal conditioning stage, an

ADC stage, and an output isolation stage. The ±10 V input

signal is level shifted and attenuated by the U1A op amp that is

one-half of the dual AD8606. The output of the op amp is 0.1 V

to 2.4 V, which matches the input range of the ADC (0 V to

2.5 V) with 100 mV headroom to maintain linearity. The

buffered voltage reference (VREF =2.5 V) from the ADC is used

to generate the required offset. Resistor values can be modified

to accommodate other popular input ranges as described later

in this circuit note.

The circuit design allows single supply operation. The minimum

output voltage specification of the AD8606 is 50 mV for a 2.7 V

power supply and 290 mV for 5 V power supply with 10 mA

load current, over the temperature range of −40°C to +125°C. A

minimum output voltage of 45 mV to 60 mV is a conservative

estimate for a 3.3 V power supply, a load current less than

1 mA, and a narrower temperature range.

Considering the tolerances of the parts, the minimum output

voltage (low limit of the range) is set to 100 mV to allow a safety

margin. The upper limit of the output range is set to 2.4 V in

order to give 100 mV headroom for the positive swing at the

ADC input. Therefore, the nominal output voltage range of the

input op amp is 0.1 V to 2.4 V.

The second half of the AD8606 (U1B) is used to buffer the

internal 2.5 V voltage reference of the AD7091R (U3) ADC.

The AD8606 is chosen for this application because of its low offset

voltage (65 μV maximum), low bias current (1 pA maximum)

and low noise (12 nV/√Hz maximum). Power dissipation is

only 9.2 mW on a 3.3 V supply.

A single-pole RC filter (R3/C9) follows the op amp output stage

to reduce the out-of-band noise. The cutoff frequency of the RC

filter is set to 664 kHz. An optional second order filter (R4, C10,

andR1,R2, C11) can be added to reduce the filter cutoff frequency

even further in case of low frequency industrial noise. In such

case, the sampling rate of the AD7091R can be reduced because

of the lower signal bandwidth.

The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its

ultralow power 349 μA at 3.3 V (1.2 mW) which is significantly

lower than any competitive ADC currently available in the market.

The AD7091R also contains an internal 2.5 V reference with

±4.5 ppm/oC typical drift. The input bandwidth is 7.5 MHz,

and the high speed serial interface is SPI compatible. The

AD7091R is available in a small footprint 10-lead MSOP.

The total power dissipation of the circuit (excluding the

ADuM5401 isolator) is approximately 10.4 mW when

operating on a 3.3 V supply.

Galvanic isolation is provided by the ADuM5401 (C-Grade)

quad channel digital isolator. In addition to the isolated output

data, the ADuM5401 also provides isolated 3.3 V for the circuit.

The ADuM5401 is not required for normal circuit operation

unless isolation is needed. The ADuM5401 quad-channel,

2.5 kV isolators with integrated dc-to-dc converter, is available

in a small 16-lead SOIC. Power dissipation of the ADuM5401

with a 7 MHz clock is approximately 140 mW.

The AD7091R requires a 50 MHz serial clock (SCLK) to achieve

a 1 MSPS sampling rate. However, the ADuM5401 (C-grade)

isolator has a maximum data rate of 25 Mbps that corresponds

to a maximum serial clock frequency of 12.5 MHz. In addition,

the SPI port requires that the trailing edge of the SCLK clock

the output data into the processor, therefore the total round-trip

propagation delay through the ADuM5401 (120 ns maximum)

limits the upper clock frequency to 1/120 ns = 8.3 MHz.

Even though the AD7091R is a 12-bit ADC, the serial data is

formatted into a 16-bit word to be compatible with the processor

serial port requirements. The sampling period, TS, therefore

consists of the AD7091R 650 ns conversion time plus 58 ns

(extra time required from data sheet, t1 delay + tQUIET delay) plus

16 clock cycles for the SPI interface data transfer.

TS = 650 ns + 58 ns + 16 × 120 ns = 2628 ns

fS = 1/TS = 1/2628 ns = 380 kSPS

In order to provide a safety margin, a maximum SCLK of

7 MHz and a maximum sampling rate of 300 kSPS is

recommended. The digital SPI interface can be connected to the

microprocessor evaluation board using the 12-pin Pmod-

compatible connector (Digilent Pmod Specifications).

Circuit Design

The circuit shown in Figure 2 attenuates and level shifts the −10 V

to +10 V input signal to the ADC input range of 0.1 V to 2.4 V.

OUTPUT

+0.1V TO +2.4V

R4

52.3kΩ

INPUT

–10V TO +10V

1

2

GND_ISO

R6

10kΩ

R5

12kΩ

R2

12kΩ

R1

52.3kΩ

GND_ISO

GND_ISO

GND_ISO

GND_ISO

U1A

1/2 AD8606

+3.3V

VREF

2.5V

Figure 2. Input Voltage Signal Conditioning Circuit