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ST10R272 Datasheet(PDF) 19 Page - STMicroelectronics |
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ST10R272 Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 77 page ![]() 19/77 ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) input ports can receive 00,0000,0000h to allow direct transfers from the B-source and A- source, respectively, to the Accumulator (case of Multiplication, Shift.). The output of the arithmetic unit goes to the Accumulator. It is also possible to saturate the Accumulator on a 32-bit value, automatically after every accumulation. Automatic saturation is enabled by setting the saturation bit MS in the MCW register. When the Accumulator is in the saturation mode and an 32-bit overflow occurs, the accumulator is loaded with either the most positive or the most negative value representable in a 32-bit value, depending on the direction of the overflow. The value of the Accumulator upon saturation is 00,7fff,ffffh (positive) or ff,8000,0000h (negative) in signed arithmetic. Automatic saturation sets the SL flag MSW. This flag is a sticky flag which means it stays set until it is explicitly reset by the user. 40-bit overflow of the Accumulator sets the SV flag in MSW. This flag is also a sticky flag. 40-bit accumulator register The 40-bit Accumulator consists of three SFR registers MAH, MAL and MAE. MAH and MAL are 16-bit wide. MAE is 8-bit wide and is contained within the least significant byte of MSW. Most co-processor operations specify the 40-bit Accumulator register as source and/or destination operand. Data limiter Saturation arithmetic is also provided to selectively limit overflow, when reading the accumulator by means of a CoSTORE <destination> MAS instruction. Limiting is performed on the MAC Accumulator. If the contents of the Accumulator can be represented in the destination operand size without overflow, the data limiter is disabled and the operand is not modified. If the contents of the accumulator cannot be represented without overflow in the destination operand size, the limiter will substitute a ‘limited’ data as explained in the following table. Note In this case, the accumulator and the status register are not affected. MAS readable from a CoSTORE instruction. Register E bit N bit Output of the Limiter x 0 x unchanged MAS 1 0 7fffh MAS 1 1 8000h Table 4 Data Limit Values 1 |
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