ST10R272 datasheet(52/77 Pages) STMICROELECTRONICS

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ST10R272L - ELECTRICAL CHARACTERISTICS

16.3.3

Multiplexed Bus

VDD = 3.3 V ± 0.3 V

VSS = 0 V

TA = -40 to +85 °C

CL = 50 pF

ALE cycle time = 6 TCL + 2

tA + tC + tF (60 ns at 50-MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 50 MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

ALE high time

7 +

–

TCL - 3 +

–ns

Address (P1, P4), BHE

setup to ALE

3 +

–

TCL - 7 +

–ns

Address (P0) setup to ALE t6m

5 +

–

TCL - 5 +

–ns

Address hold after ALE

5 +

–

TCL - 5 +

–ns

ALE falling edge to RD,

WR (with RW-delay)

5 +

–

TCL - 5 +

–ns

ALE falling edge to RD,

WR (no RW-delay)

-5 +

–

-5 +

–ns

Address float after RD,

(with RW-delay)1)

t10

–

Address float after RD,

(no RW-delay)1

t11

–

151

–

TCL + 51

RD, WR low time

(with RW-delay)

t12

13 +

–

2TCL - 7+

–ns

RD, WR low time

(no RW-delay)

t13

23 +

–

3TCL - 7 +

–ns

RD to valid data in

(with RW-delay)

t14

–

5 +

–

2TCL - 15

RD to valid data in

(no RW-delay)

t15

–

15 +

–

3TCL - 15

ALE low to valid data in

t16

–

tA + tC

–

3TCL - 15

tA + tC

Address to valid data in

t17

–

+ 2

tA + tC

–

4TCL - 20

+ 2

tA + tC

Table 17 Multiplexed bus

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