ST10R272 datasheet(22/77 Pages) STMICROELECTRONICS

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ST10R272L - INTERRUPT AND TRAP FUNCTIONS

Number representation & rounding

The MAC supports the two’s-complement representation of binary numbers. In this format,

the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to

one for negative numbers. Unsigned numbers are supported only by multiply/multiply-

accumulate instructions which specifies whether each operand is signed or unsigned.

In two’s complement fractional format, the N-bit operand is represented using the 1.[N-1]

format (1 signed bit, N-1 fractional bits). Such a format can represent numbers between -1

and +1-2-[N-1]. This format is supported when MP of MCW is set.

The MAC implements ‘two’s complement rounding’. With this rounding type, one is added to

the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared).

INTERRUPT AND TRAP FUNCTIONS

The architecture of the ST10R272L supports several mechanisms for fast and flexible

response to the service requests that can be generated from various sources, internal or

external to the microcontroller. Any of these interrupt requests can be programmed to be

serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In a standard interrupt service, program execution is suspended and a branch to the interrupt

service routine is performed. For a PEC service, just one cycle is ‘stolen’ from the current

CPU activity. A PEC service is a single, byte or word data transfer between any two memory

locations, with an additional increment of either the PEC source or the destination pointer. An

individual PEC transfer counter is decremented for each PEC service, except in the

continuous transfer mode. When this counter reaches zero, a standard interrupt is performed

to the corresponding source-related vector location. PEC services are very well suited, for

example, to the transmission or reception of blocks of data. The ST10R272L has 8 PEC

channels, each of which offers fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag

and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related

having been accepted by the CPU, an interrupt service can only be interrupted by a higher

priority service request. For standard interrupt processing, each of the possible interrupt

sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision

requirements. These fast interrupt inputs, feature programmable edge detection (rising edge,

falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number.

ST10R272 Datasheet(PDF) 22 Page - STMicroelectronics