ST40RA datasheet(79/94 Pages) STMICROELECTRONICS

79 / 94 page

A Interconnect architecture

ST40RA

79/94

STMicroelectronics

ADCS 7260755H

A.1

Arbitration schemes

A.1.1

PCI arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) for fixed priority mode has to be in the following priority order:

CPU buffer,

EMPI,

GPDMA,

PCI (PCI master request, although not expected, get served to avoid deadlock).

The priority orders have to be programmable and the latency checking algorithm can be enabled for

GPDMA, PCI, EMPI.

A.1.2

EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI)

The default configuration (after reset) for fixed priority mode has to be in the following priority order:

CPU buffer,

PCI,

EMPI,

GPDMA.

The priority order have to be programmable and the latency checking algorithm can be enabled for

GPDMA, PCI, EMPI.

A.1.3

LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) as to be to work fixed priority mode in the following priority

order:

CPU,

GPDMA and PCI buffer.

The priority orders have to be programmable and the latency checking algorithm can be enabled for

GPDMA, PCI, EMPI.

A.1.4

PER arbiter: (CPU, GPDMA, PCI, EMPI)

The default configuration (after reset) as to be to work fixed priority mode in the following priority

order:

CPU buffer,

PCI,

EMPI,

GPDMA.

The priority order have to be programmable and the latency checking algorithm can be enabled for

GPDMA, PCI, EMPI.

ST40RA Datasheet(PDF) 79 Page - STMicroelectronics

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